

// Language: Verilog 2001


/*--------------------------------------------------------------------------------------------------------------------------*                 
//------------------------------------------------  bus 连接线 -------------------------------------------------------
                 
// bus slave 0 wire 
wire [7:0] s0_dat  ; 
wire [7:0] s0_rdt  ; 
wire [7:0] s0_adr ;  
wire s0_wen ;
wire [7:0] s0_addr;    // Slave address prefix
wire [7:0] s0_addr_msk; // Slave address prefix mask
                 
// bus slave 1 wire 
wire [7:0] s1_dat  ; 
wire [7:0] s1_rdt  ; 
wire [7:0] s1_adr ;  
wire s1_wen ;
wire [7:0] s1_addr;    // Slave address prefix
wire [7:0] s1_addr_msk; // Slave address prefix mask   

//------------------------------------------------  bus 地址分配 -------------------------------------------------------
assign {s0_addr , s0_addr_msk } = {8'h00 , 8'hf0} ;
assign {s1_addr , s1_addr_msk } = {8'h10 , 8'hf0} ;  
                            
例化模板:
bus_mux_2 u_bus_mux_2  (
    .clk( ) , 
    .rst_n( ) ,
    .m_dat_i( )  ,  
    .m_dat_o( ) ,   
    .m_adr_i( ) , 
    .m_wen_i( )    ,
                 
    //bus slave 0 output          
    .s0_dat_o( s0_dat)  , 
    .s0_dat_i( s0_rdt)  , 
    .s0_adr_o( s0_adr) , 
    .s0_wen_o( s0_wen)  ,
                 
    //bus slave 0 address configuration
    .s0_addr    ( s0_addr), // Slave address prefix
    .s0_addr_msk( s0_addr_msk), // Slave address prefix mask
                 
    //bus slave 1 output          
    .s1_dat_o( s1_dat)  , 
    .s1_dat_i( s1_rdt)  , 
    .s1_adr_o( s1_adr) , 
    .s1_wen_o( s1_wen)  ,
                 
    //bus slave 1 address configuration
    .s1_addr    ( s1_addr), // Slave address prefix
    .s1_addr_msk( s1_addr_msk)  // Slave address prefix mask
)            
\*--------------------------------------------------------------------------------------------------------------------------*/

                 
 `timescale 1 ns / 1 ps
`ifndef  __bus_mux_2__
`define  __bus_mux_2__
                 
/*
 * bus 2 port multiplexer
 */
module bus_mux_2 
(
    input  wire                    clk,
    input  wire                    rst_n,

    /*
     *  master input
     */             
    input  wire [7:0]  m_dat_i  ,  
    output wire [7:0]  m_dat_o  ,   
    input  wire [7:0]  m_adr_i , 
    input  wire        m_wen_i    ,

    /*
     * slave 0 output
     */
    output  wire [7:0]  s0_dat_o  , 
    input   wire [7:0]  s0_dat_i  , 
    output  wire [7:0]  s0_adr_o , 
    output  wire        s0_wen_o  ,
                 
    /*
     * slave 0 address configuration
     */
    input  wire [7:0]   s0_addr,     // Slave address prefix
    input  wire [7:0]   s0_addr_msk, // Slave address prefix mask

    /*
     * slave 1 output
     */
    output  wire [7:0]  s1_dat_o  , 
    input   wire [7:0]  s1_dat_i  , 
    output  wire [7:0]  s1_adr_o , 
    output  wire        s1_wen_o  ,
                 
    /*
     * slave 1 address configuration
     */
    input  wire [7:0]   s1_addr,     // Slave address prefix
    input  wire [7:0]   s1_addr_msk  // Slave address prefix mask
);

wire s0_sel = ~|((m_adr_i ^ s0_addr) & s0_addr_msk);
wire s1_sel = ~|((m_adr_i ^ s1_addr) & s1_addr_msk);


// wire s0_sel = s0_match;
// wire s1_sel = s1_match & ~(s0_match);


// master
assign m_dat_o = s0_sel ? s0_dat_i :
                  s1_sel ? s1_dat_i :
                  8'h0;
                 
// assign m_dat_o = s0_dat_i|s1_dat_i ;   

// slave 0
assign s0_adr_o = m_adr_i & ~s0_addr_msk ; 
assign s0_dat_o  = m_dat_i ; 
assign s0_wen_o  = m_wen_i & s0_sel ;

// slave 1
assign s1_adr_o = m_adr_i & ~s1_addr_msk ; 
assign s1_dat_o  = m_dat_i ; 
assign s1_wen_o  = m_wen_i & s1_sel ;


endmodule

`endif 